The LNM Institute of Information Technology

Kusum Lata

kusum@lnmiit.ac.in

Date of joining:

13-12-2013

Department:

Electronics and Communication Engineering

Summary

Kusum Lata is a faculty member in the department of ECE and working in the domain on VLSI Design, and now a days focuses on Hardware Accelerator Design for AI and Hardware Security.

Biography

Kusum Lata, a Senior Member of IEEE and ACM, holds a master’s degree from IIT Roorkee (2003) and a Ph.D. from IISc Bangalore (2010). During her Ph.D., she interned at Intel India Pvt Ltd, receiving the "Spontaneous Recognition Award." She served as a Lecturer at IIIT-A for three years and currently works as an Associate Professor at LNMIIT, Jaipur. Previously, she was an Assistant Professor at LNMIIT. She received the "Outstanding Research Paper Award" at ASQED-2009. Her research focuses on FPGA-based designs, hardware accelerators for AI, cryptographic algorithms, and hardware security.

Research Area

Digital System Design using FPGAs, Design for Testability, Hardware Security, Hardware Implementation of Cryptographic Algorithms, Hardware Implementation of Deep Learning Algorithms.

Personal information

Name

Designation

Department

ORCID

Scopus_link

Website

Dr. Kusum Lata

Professor

Electronics and Communication Engineering

https://orcid.org/0000-0003-3681-2791

https://www.scopus.com/authid/detail.uri?authorId=35743015300

Education

	Degree/Diploma	Institute/ Organization	Year	Branch/Specialization
1	Ph. D. Doctor of Philosophy	Indian Institute of Science (IISc), Bangalore	2010	VLSI
2	M. Tech. Master of Technology	IIT Roorkee	2003	SSEM
3	M.Sc. Master of Science	IIT Roorkee	2001	Physics

Experience

	Name of Organization	Post/Designation	Duration From	Duration To
1	Indian Institute of Information Technology, Allahabad (IIIT-A)	Lecturer	2010	2013
2	Intel India Pvt. Ltd. Bangalore	Semester Long Research Intern	2005	2005

Publications

1	Chhabra, S., Lata, K., Obfuscated AES cryptosystem for secure medical imaging systems in IoMT edge devices. Health Technol. (2022). AUG 2022, Obfuscated AES cryptosystem for secure medical imaging systems in IoMT edge devices. Health Technol. (2022). AUG 2022 ,
2	Chhabra, S, Lata, K, . Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications. Concurrency Computat Pract Exper. 2022; 34( 21):e7058. MAY 2022, . Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications. Concurrency Computat Pract Exper. 2022; 34( 21):e7058. MAY 2022 ,
3	Chhabra, S., Lata, K, Hardware Obfuscation of AES IP Core Using PUFs and PRNG: A Secure Cryptographic Key Generation Solution for Internet-of-Things Applications. SN COMPUT. SCI. 3, 303 (2022) MAY 2022, Hardware Obfuscation of AES IP Core Using PUFs and PRNG: A Secure Cryptographic Key Generation Solution for Internet-of-Things Applications. SN COMPUT. SCI. 3, 303 (2022) MAY 2022 IndexedIn : [Scopus] DOI : https://doi.org/10.1007/s42979-022-01194-x,
4	Chhabra, S, Lata, K, Towards the enhancement of AES IP security using hardware obfuscation technique, Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT. Security and Privacy. 2022; 5( 4):e233. APRIL 2022 IndexedIn : [WoS] DOI : doi:10.1002/spy2.233,
5	K. Lata, S. Chhabra and S. Saini, "Hardware–Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment,", "Hardware–Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment," in IEEE Consumer Electronics Magazine, vol. 11, no. 4, pp. 92-97. SEPT 2021 IndexedIn : [WoS] DOI : doi: 10.1109/MCE.2021.3115999.,
6	Nandit Kaushik and Kusum Lata, "An Approach Towards Resisting Side-Channel Attacks for Secured Testing of Advanced Encryption Algorithm (AES) Cryptochip", "An Approach Towards Resisting Side-Channel Attacks for Secured Testing of Advanced Encryption Algorithm (AES) Cryptochip", ISEA-ISAP 2020: Third ISEA International Conference on Security and Privacy, February 27-March 1, 2020, IIT Guwahati, Guwahati, Assam FEB 2020 ,
7	Surbhi Chhabra, Vishakha Dhanwani, Vikas Kumar Dhaka and Kusum Lata,, "Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems", "Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems" 24th International Symposium on VLSI Design and Test, July 23-25, 2020, IIT Bhubaneswar, Odisha, India JULY 2020 ,
8	Surbhi Chhabra and Kusum Lata, "Key-based Obfuscation using Strong Physical Unclonable Function: A Secure Implementation", "Key-based Obfuscation using Strong Physical Unclonable Function: A Secure Implementation", 15th International Conference on Information assurance and security (IAS-2019) VIT University, Bhopal, India, December 11-12, 2019 DEC 2019 ,
9	Aastha Bhardwaj, Surbhi Chhabra and Kusum Lata , "FPGA Implementation of Traffic Light Controller and Its Analysis in the Presence of Hardware Trojan", "FPGA Implementation of Traffic Light Controller and Its Analysis in the Presence of Hardware Trojan" in the IEEE 7th International Conference on Advances in Computing, Communication and Informatics (ICACCI-2018), September 19-22, 2018, Bangalore, India. SEPT 2018 ,
10	Mohita Jaiswal and Kusum Lata , "Hardware Implementation of Text Encryption using Elliptic Curve Cryptography over 192 bit Prime Field", "Hardware Implementation of Text Encryption using Elliptic Curve Cryptography over 192 bit Prime Field" in the IEEE 7th International Conference on Advances in Computing, Communication and Informatics (ICACCI-2018), September 19-22, 2018, Bangalore, India. SEPT 2018 ,
11	Surbhi Chhabra and Kusum Lata , "Enhancing Data Security using Obfuscated 128-bit AES Algorithm - An Active Approach at RTL Level", "Enhancing Data Security using Obfuscated 128-bit AES Algorithm - An Active Approach at RTL Level" in the IEEE 7th International Conference on Advances in Computing, Communication and Informatics (ICACCI-2018), September 19-22, 2018, Bangalore, India. SEPT 2018 ,
12	Surbhi Chhabra and Kusum Lata, "Design and Analysis of Logic Encryption Based 128-Bit AES Algorithm: A Case Study,", 15th IEEE India Council International Conference (INDICON 2018), December 16-18, Amrita Vishwa Vidyapeetham, Coimbatore, 2018 . DEC 2018 ,
13	Surbhi Chhabra and Kusum Lata,, "Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications,“, "Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications,“ IEEE 4th International Symposium on Smart Electronic Systems ( iSES 2018 ), December 17-19, Hyderabad, 2018. DEC 2018 ,
14	Priyanka Gupta, Sandeep Saini, Kusum Lata, " Securing QR codes by RSA on FPGA", " Securing QR codes by RSA on FPGA" in IEEE 6th International Conference on Advances in Computing, Communications and Informatics (ICACCI - 2017) to be held in Manipal University, Karnatka, India, 13-16 September, 2017. SEPT 2017 ,
15	Surbhi Chhabra, Kusum Lata,, "Analysis of AES Cryptosystem in the Existence of Hardware Trojan", "Analysis of AES Cryptosystem in the Existence of Hardware Trojan" in IEEE 6th International Conference on Advances in Computing, Communications and Informatics (ICACCI - 2017) to be held in Manipal University, Karnatka, India, 13-16 September, 2017. SEPT 2017 ,
16	Ayushparth Sharma and Kusum Lata,, "Analysis of AES Cryptosystem in the Existence of Hardware Trojan", "Analysis of AES Cryptosystem in the Existence of Hardware Trojan" in IEEE 6th International Conference on Advances in Computing, Communications and Informatics (ICACCI - 2017) to be held in Manipal University, Karnatka, India, 13-16 September, 2017. SEPT 2017 ,
17	Ayushparth Sharma and Kusum Lata,, ,“ Low-Leakage and Process-Variation-Tolerant Write-Read Disturb-Free 9T SRAM Cell Using CMOS and FinFETs”,, ,“ Low-Leakage and Process-Variation-Tolerant Write-Read Disturb-Free 9T SRAM Cell Using CMOS and FinFETs”, 17th International Symposium on Quality Electronic Design (ISQED - 2016), March 14-16, 2016, Santa Clara, CA, United States. 2016 ,
18	Kusum Lata and Akshay Mann,, “Assertion Based Functional Verification Analysis of AMBA-AHB using System Verilog”,, “Assertion Based Functional Verification Analysis of AMBA-AHB using System Verilog”, International Journal of Circuits and Architecture Design (IJCAD), ISSN: 2051-7025 (Print), 2051-7033 (Online), Publisher: Inderscience Publishers, 2014, Vol. 1, no. 2, pp. 174-192. 2014 ,
19	Kusum Lata and Subir K Roy,, “Formal Verification of Analog and Mixed Signal Designs using SPICE Circuit Simulation Traces’, “Formal Verification of Analog and Mixed Signal Designs using SPICE Circuit Simulation Traces’, in Special Issue on Verification and Testing Challenges in Future Microprocessor and SoC Designs of Journal of Electronic Testing: Theory and Applications (JETTA),ISSN: 0923-8174 (print version), ISSN: 157300727 (electronic version), Journal no. 10836, Publisher: Springer, Volume 29, Issue 5, pp 715- 740, October 2013. OCT 2013 IndexedIn : [Scopus,WoS,UGC CARE List] DOI : https://doi.org/10.1007/s10836-013-5407-7,
20	Kusum Lata and Manoj Kumar, “All Digital Phase-Locked Loop (ADPLL): A Survey”, International Journal of Future Computer and Communication (IJFCC, ISSN: 2010-3751), Vol. 2, No. 6, pp 551-555, 2013. 2013 ,
21	Kusum Lata and Manoj Kumar, “FPGA Implementation of FSK Decoder using ADPLL”, Proceedings of IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing (iMac4s- 2013), March 22-23, 2013 , Kerala, India. 2013 ,
22	Kusum Lata and Manoj Kumar,, , “ADPLL Design and Implementation on FPGA”, Proceedings of IEEE International Conference on Intelligent Systems and Signal Processing (ISSP-2013), March 1-2, 2013, Gujarat, India. 2013, , “ADPLL Design and Implementation on FPGA”, Proceedings of IEEE International Conference on Intelligent Systems and Signal Processing (ISSP-2013), March 1-2, 2013, Gujarat, India. 2013 ,
23	Manoj Kumar and Kusum Lata, “FPGA Implementation of ADPLL with Ripple Reduction Techniques”,, , “FPGA Implementation of ADPLL with Ripple Reduction Techniques”, International Journal of VLSI Design & Communication Systems (VLSICS, ISSN: 0976 - 1527), Vol. 3, No. 2, pp 99 – 106, April 2012. 2012 ,
24	Manoj Kumar and Kusum Lata, , “ALL Digital Phase-Locked Loop (ADPLL): A Survey”,, “ALL Digital Phase-Locked Loop (ADPLL): A Survey”, Proceedings of the 4th International Conference on Electronics Computer Technology (ICECT 2012), April 6-8, 2012, Kanyakumari, India. 2012 ,
25	Jairam Sukumar, Subir K Roy, Kusum Lata and Navakanta Bhat , “Formal Verification of Hybrid Automotive Systems”, “Formal Verification of Hybrid Automotive Systems” Motion Control, Federico Casolo (Ed.), ISBN: 978-953-7619-55-8, p.p.141-162, Publisher: InTech, 2010. 2010 ,
26	Kusum Lata, H S Jamadagni, “Formal Verification of Full Wave Rectifier using SPICE Simulation Traces” 11th International Symposium on Quality Elecronic Design (ISQED 2010), March 22-24, 2010, San Jose, CA, USA. 2010, “Formal Verification of Full Wave Rectifier using SPICE Simulation Traces” 11th International Symposium on Quality Elecronic Design (ISQED 2010), March 22-24, 2010, San Jose, CA, USA. 2010 ,
27	Kusum Lata, H S Jamadagni, , “Formal Verification of Tunnel Diode Oscillator with Temperatures”, “Formal Verification of Tunnel Diode Oscillator with Temperatures”, 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Jan. 18-21, 2010, Taipei, Taiwan. 2010 ,
28	Kusum Lata, H S Jamadagni,, “Formal Verification of Full Wave Rectifier: A Case Study”, “Formal Verification of Full Wave Rectifier: A Case Study”, IEEE 8th International Conference on ASIC (IEEE ASICON 2009), October 20-23, 2009-Changsha, China. 2009 ,
29	Kusum Lata, Subir K Roy, H S Jamadagni, “Towards Formal Verification of Analog Mixed Signal Designs using SPICE Circuit Simulation Traces”, “Towards Formal Verification of Analog Mixed Signal Designs using SPICE Circuit Simulation Traces”, 1st Asia Symposium on Quality Electronic Design, July 15-16 2009, KL, Malaysia (Outstanding Research Paper Award) 2009 ,
30	Jairam S., Kusum Lata, Subir K. Roy and Navakanta Bhat, “Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches”, “Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches”, Proceedings of 15th IEEE International Conference on Electronics, Circuits and Systems, Aug-Sep,2008 ( ICECS 2008 ), Malta. 2008 ,
31	Kusum Lata, Jairam Sukumar, Subir Roy, H S Jamadagni, “Case Studies Towards a Platform Independent Framework for Formal Verification of Hybrid Systems”, “Case Studies Towards a Platform Independent Framework for Formal Verification of Hybrid Systems” 12th IEEE VLSI Design And Test Symposium (VDAT), July 23-26 2008, Bangalore, India. 2008 ,
32	Jairam S., Kusum Lata, Subir K. Roy and Navakanta Bhat, “Formal Verification of a MEMS Based Adaptive Cruise Control System”, Proceedings of 11th International Conference on Modeling and Simulation of Micro Systems, June 2008, Boston, USA 2008, “Formal Verification of a MEMS Based Adaptive Cruise Control System”, Proceedings of 11th International Conference on Modeling and Simulation of Micro Systems, June 2008, Boston, USA 2008 ,

Workshop attended

	Type	Month	Year	Information
1	Short Term Course	July	2015	AICTE sponsored One Week Short Term Course on " Recent Advances in Nanobiophotonics (From Lab to Clinic)" from July 13 - 17, 2015, organized by Indian Institute of Technology (IIT), Roorkee.
2	Workshop	February	2014	Four Days Workshop on "Outcome Based Accreditation Process" on 3rd, 17th, 18th & 19th February, 2014, organized by the National Board of Accreditation, New Delhi at Nodal Centre, The LNM Institute of Information Technology, Jaipur, Rajasthan.
3	Short Term Course	September	2014	One Week Faculty Development Program from 22 September- 27 September, 2014 at Microsoft Office, Bangalore, India
4	Training	June	2014	Two weeks, International Summer & Winter Term on " Advanced Formal Techniques in Design, Verification and Testing of Digital Integrated Circuits" from June 16 - June 27, 2014, organized by Indian Institute of Technology, Kharagpur.
5	Training	June	2012	Three-week UGC-NRCPS sponsored Summer School on “Techniques for Design, Fabrication and Computation of Integrated Circuits – TECHNOMICS-12”, organized by Institute of Radio Physics and Electronics, University of Calcutta (A UGC Networking Resource Centre in Physical Sciences), from May 23 to June 13, 2012.
6	Workshop	March	2012	MOS-AK/GSA India2012- International Workshop on “Device Modeling of Microsystems”, organized by Indian National Academy of Engineering (INAE) on March 16-18 2012 at Jaypee Institute of Information Technology, Noida.
7	Workshop	December	2011	10-days ISTE workshop on “Solar Photovoltaics: Fundamentals, Technologies and Applications” under the National Mission on Education through ICT (MHRD, Govt. of India) and Ministry of New and Renewable Energy organized by IIT- Bombay from December 12 to December 22, 2011.
8	Conference - National	January	2010	15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), January 18 - 21, 2010, Taipei, Taiwan.
9	Conference - International	October	2009	The IEEE 8th International Conference on ASIC (IEEE ASICON 2009), October 20-23, 2009-Changsha, China.
10	Conference - National	July	2009	1st Asia Symposium on Quality Electronic Design (IEEE ASQED 2009), July 15-16 2009, Kula Lumpur, Malaysia.
11	Training	July	2008	12th IEEE VLSI Design and Test Symposium (VDAT 2008), July 23-26, 2008, Wipro Campus, Electronics City, Hosur Road, Bangalore, India.
12	Workshop	January	2007	Two-day workshop on “Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems” organized by General Motors R&D, India Science Lab on January 5-6 2007 at the NIAS auditorium, IISc campus, Bangalore, India.
13	Conference - International	January	2007	20th IEEE International conference on VLSI Design, January 6-10, 2007, Bangalore, India.
14	Workshop	January	2006	Two-Day workshop on “Electronics System Level Design” organized by VLSI society of India and IEEE Circuits and Systems Society (Bangalore Chapter) on January 9-10, 2006 at Indian Institute of Science (IISc) ,Bangalore, India.
15	Workshop	February	2005	Two-Day workshop on “Low Power Design Techniques” organized by VLSI society of India, IEEE Circuits and Systems Society (Bangalore Chapter) and IEEE Electron Devices and Solid State Circuits Society (Bangalore Chapter) on February 25-26, 2005 at Indian Institute of Science (IISc) ,Bangalore, India.

Workshop conducted

	Type	Month	Year	Information
1	Training	March	2018	FDP on Advances in VLSI and Embedded Systems from 29th March to 2nd April, 2018 Jointly with EICT Academy MNIT Jaipur.
2	Training	June	2017	SUMMER INTERNSHIP CUM TRAINING PROGRAM ON VLSI AND EMBEDDED SYSTEMS DESIGN,19TH JUNE TO 14TH JULY 2017 at LNMIIT Jaipur
3	Workshop	June	2016	SUMMER INTERNSHIP CUM TRAINING PROGRAM ON VLSI AND EMBEDDED SYSTEMS DESIGN,13TH JUNE TO 10TH JULY 2016 at LNMIIT Jaipur
4	Conference - National	August	2016	2 Days workshop on ASIC Design Flow using Mentor Graphics Tools, in association with CoreEL India Pvt. Ltd, from 30 August to 31 August, 2016
5	Workshop	January	2015	Convenor for Three days Workshop on "Modeling, Simulation and Computational Techniques" held at LNMIIT Jaipur from January 15-17, 2015
6	Workshop	September	2015	Coordinator for Three days National Workshop on " "VLSI and Embedded Systems Design using Xilinx Vivado Design Suite & Zybo SoC" (VESD-2015) from September 25 - 27, 2015, in association with CoreEl Technologies Pvt. Ltd and Xilinx.
7	Conference - International	July	2012	Organizing Committee member for “One Day National Workshop on Electronics System Design & Manufacturing (ESDM)” on 18th July’2012, Organized By IIIT- Allahabad & Sponsored by DIT, Ministry of Communications and IT (MCIT), Govt. of India.
8	Workshop	September	2012	Organizing Committee member for International Workshop on Antenna and RF Section Design for Low Power Applications, September 27-30, 2012 Organized By IIIT- Allahabad & Co-Sponsored by IEEE UP Section.
9	Workshop	November	2012	Two Days National Workshop on “Timing Analysis of Digital VLSI Circuits” held on November 3 - 4, 2012, organized by Indian Institute of Information Technology, Allahabad (IIIT-A), sponsored by Department of Electronics and Information Technology (DeitY), Ministry of Communications & Information Technology ( MCIT ) , Govt. of India, New Delhi
10	Conference - National	December	2012	Organizing Committee Member for “Science Conclave 2012” (A Science Popularization Program), A Joint Initiative of MHRD & DST, Govt. of India, organized by IIIT-Allahabad.
11	Training	December	2011	Organizing Committee Member for “Science Conclave 2011” (A Science Popularization Program), A Joint Initiative of MHRD & DST, Govt. of India, organized by IIIT-Allahabad.
12	Conference - National	December	2010	Organizing Committee Member for “Science Conclave 2010” (A Science Popularization Program), A Joint Initiative of MHRD & DST, Govt. of India, organized by IIIT-Allahabad.